1. Field of the Invention
The present invention relates to a pulse edge selection circuit which generates pulses of desired pulse timing and desired pulse width using a multiphase clock, and more particularly, to a pulse edge selection circuit which uses a delay locked loop circuit as well as to a pulse generation circuit, sample-hold circuit, and solid-state image sensor which use the pulse edge selection circuit.
2. Description of the Related Art
Semiconductor devices including solid-state image sensors are becoming increasingly fast, requiring ever more subtle adjustments of phase relationships among their drive pulses. Japanese Patent Laid-Open No. 2009-044579 (D1) discloses a pulse edge selection circuit which adjusts pulse edge timing by means of register settings. The circuit disclosed in D1 selects a clock from a multiphase clock on a tournament basis using a transfer gate.
However, the clock selection method using a tournament-based selector such as disclosed in D1 drives even unselected logic gates such as a buffer when inputting clocks thereto, resulting in increased power consumption. For example, to select one clock from N clocks, N/2 clocks are selected by the logic gates in the first stage. Next, N/4 clocks are selected by the logic gates in the second stage, and subsequently narrowed down to one clock by the logic gate in an output stage. Therefore, at least N−1 (=N/2+N/4+. . . +1) logic gates are put into operation by the clocks. When a clock is input to a logic gate, power consumption of the logic gate is increased accordingly due to a through current and the like. Thus, a tournament-based clock selection circuit consumes a large amount of power because a large number of logic gates are simultaneously put into operation. Examples of the logic gate as referred to herein include a NAND gate, NOR gate, inverter, buffer, tristate inverter, tristate buffer, and transfer gate.